SRE :(1 Post)
Eligibility : BE/BTECH/MTECH in EE/CSE with 3-5 years handson experience in VHDL, VERILOG and FPGAs.
Salary : Consolidated salary Rs.60000/- p.m. + HRA
Job Profile : Working on high speed FPGA design and logic. Design next gen telecom system
RA: (1 Post)
Eligibility : BE/BTECH in EE/CSE with 2-4 years experience in digital design, VHDL, VERILOG, PCB design, ORCAD tools
Salary : Consolidated salary Rs.50000/- p.m. + HRA
Job Profile : Hardware design for telecom applications and building new products in the telecom domain
The positions are temporary initially for a period of one year and tenable only for the duration of project. The selection committee may offer lower or higher designation and lower or higher salary depending upon the experience and performance of the candidate in the interview. Our Website http://www.ircc.iitb.ac.in/IRCC-Webpage/rnd/JobOpportunities.jsp
Last Date of the receipt of the application is 30th August, 2018-2019.
IRCC-Webpage/rnd/HRMSLoginPage.jsp , if there is any problem applying online, send in the prescribed Application Form available at http://www.ircc.iitb.ac.in/IRCC-Webpage/rnd/PDF/Application_online.pdf Candidates can apply for multiple positions with separate Application Form for each position.
The postal address to send the application is as given below.
Assistant Registrar (R & D Office), IRCC Wing, SJMSOM Building, Indian Institute of Technology Bombay, Powai, Mumbai-400076, Phone: 022-2576 4078